インテルのみ表示可能 — GUID: mwh1409959593258
Ixiasoft
1.4.1.1. 同期メモリーブロックの使用
1.4.1.2. サポートされていないリセットおよび制御条件の回避
1.4.1.3. Read-During-Write動作の確認
1.4.1.4. RAMの推論と実装の制御
1.4.1.5. 古いデータのRead-During-Write動作を備えたシングルクロック同期RAM
1.4.1.6. 新しいデータのRead-During-Write動作を備えたシングルクロック同期RAM
1.4.1.7. Verilog HDLシンプル・デュアル・ポートおよびデュアル・クロック同期RAM
1.4.1.8. トゥルー・デュアル・ポート同期RAM
1.4.1.9. 混合幅デュアルポートRAM
1.4.1.10. バイトイネーブル信号付きRAM
1.4.1.11. 電源投入時に初期メモリーの内容の指定
2.3.6.1. インテル® Hyperflex™ Retimer Readiness (HRR)のルール
2.3.6.2. Timing Closure (TMC)のルール
2.3.6.3. Clock Domain Crossing (CDC)tルール
2.3.6.4. プラットフォーム・デザイナー Interface (PDI)のルール
2.3.6.5. Clock(CLK)のルール
2.3.6.6. Reset(RES)のルール
2.3.6.7. Non-Synchronous Structure(NSS)のルール
2.3.6.8. Signal Race (SGR)のルール
2.3.6.9. Floorplanning (FLP)のルール
2.3.6.1.1. HRR-10003: Registers on High Fan-Out Non-Global Nets
2.3.6.1.2. HRR-10004: High Fan-out Non-Global Nets
2.3.6.1.3. HRR-10101: Asynchronous Clears
2.3.6.1.4. HRR-10107: Maximum Fan-out for Signal
2.3.6.1.5. HRR-10115: High Fan-out Signal
2.3.6.1.6. HRR-10201: Power Up Don't Care Setting May Prevent Retiming
2.3.6.1.7. HRR-10203: Register Power-Up Settings Conflict with Device Settings
2.3.6.1.8. HRR-10204: Reset Release Instance Count Check
2.3.6.2.1. TMC-20001: Timing Paths With Impossible Hold Requirement
2.3.6.2.2. TMC-20002: Timing Paths with Removal Slack Exceeding Threshold
2.3.6.2.3. TMC-20004: Timing Paths with Setup Slack Exceeding Threshold
2.3.6.2.4. TMC-20005: Timing Paths with Recovery Slack Exceeding Threshold
2.3.6.2.5. TMC-20006: Unregistered User-Partition Inputs
2.3.6.2.6. TMC-20007: Unregistered Paths Between User-Partitions
2.3.6.2.7. TMC-20010: Logic Level Depth
2.3.6.2.8. TMC-20011: Missing Input Delay
2.3.6.2.9. TMC-20012: Missing Output Delay
2.3.6.2.10. TMC-20013: Partial Input Delay
2.3.6.2.11. TMC-20014: Partial Output Delay
2.3.6.2.12. TMC-20015: Inconsistent Min-Max Delay
2.3.6.2.13. TMC-20016: Invalid Reference Pin
2.3.6.2.14. TMC-20017: Loops Detected
2.3.6.2.15. TMC-20018: Latches Detected
2.3.6.2.16. TMC-20019: Partial Multicycle Assignment
2.3.6.2.17. TMC-20020: Invalid Multicycle Assignment
2.3.6.2.18. TMC-20021: Partial Min-Max Delay Assignment
2.3.6.2.19. TMC-20022: Incomplete I/O Delay Assignment
2.3.6.2.20. TMC-20050: RAM Control Signals Driven by LUTs or ALMs instead of DFFs
2.3.6.2.21. TMC-20051: RAM Control Signals Driven by High Fan-Out Net
2.3.6.2.22. TMC-20052: Inferred Latch Count Check
2.3.6.2.23. TMC-20200: Setup-Failing Paths with Impossible Requirements
2.3.6.2.24. TMC-20201: Setup-Failing Paths with High Clock Skew
2.3.6.2.25. TMC-20202: Setup-Failing Paths with High Logic Delay
2.3.6.2.26. TMC-20203: Setup-Failing Paths with High Fabric Interconnect Delay
2.3.6.2.27. TMC-20204: Setup-Failing Path Endpoints with Retiming Restrictions
2.3.6.2.28. TMC-20205: Setup-Failing Path Endpoints with Explicit Power-Up States Can Restrict Retiming
2.3.6.2.29. TMC-20500: Hierarchical Tree Duplication was Shallower than Possible
2.3.6.2.30. TMC-20501: Hierarchical Tree Duplication was Shallower than Requested
2.3.6.2.31. TMC-20550: Automatically-Discovered Duplication Candidate Rejected for Placement Constraint
2.3.6.2.32. TMC-20551: Automatically-Discovered Duplication Candidate Likely Requires More Duplication
2.3.6.2.33. TMC-20552: User-Directed Duplication Candidate was Rejected
2.3.6.2.34. TMC-20601: Registers with High Immediate Fan-Out Tension
2.3.6.2.35. TMC-20602: Registers with High Timing Path Endpoint Tension
2.3.6.2.36. TMC-20603: Registers with High Immediate Fan-Out Span
2.3.6.2.37. TMC-20604: Registers with High Timing Path Endpoint Span
2.3.6.5.1. CLK-30001: Gated Clock is Not Feeding at Least a Predefined Number of Clock Ports to Effectively Save Power
2.3.6.5.2. CLK-30002:クロック・ピン以外のピンをドライブするクロック
2.3.6.5.3. CLK-30026: Missing Clock Assignment
2.3.6.5.4. CLK-30027: Multiple Clock Assignment
2.3.6.5.5. CLK-30028: Invalid Generated Clock
2.3.6.5.6. CLK-30029: Invalid Clock Assignments
2.3.6.5.7. CLK-30030: PLL Setting Violation
2.3.6.5.8. CLK-30031: Input Delay Assigned to Clock
2.3.6.6.1. RES-30131: Reset Nets with Polarity Conflict
2.3.6.6.2. RES-30132: Registers May Not Be Properly Reset
2.3.6.6.3. RES-30133: Embedded Memory Blocks with Initialized Content That Might be Affected by Spurious Writes
2.3.6.6.4. RES-50001: Asynchronous Reset Is Not Synchronized
2.3.6.6.5. RES-50002: Asynchronous Reset is Insufficiently Synchronized
2.3.6.6.6. RES-50003: Asynchronous Reset Missing Timing Constraint
2.3.6.6.7. RES-50004: Multiple Asynchronous Resets within Reset Synchronizer Chain
2.3.6.6.8. RES-50005: RAM Control Signals Driven by Flops with Asynchronous Clears
2.3.6.7.1. NSS-30011: Design Contains Combinational Loops
2.3.6.7.2. NSS-30012: Design Contains Latches
2.3.6.7.3. NSS-30013: Design Contains Ripple Clock Structures
2.3.6.7.4. NSS-30014: Asynchronous Pulse Generators
2.3.6.7.5. NSS-30015: Multiple Pulses Generated in the Design
2.3.6.7.6. NSS-30016: Design Contains SR Latches
2.3.6.7.7. NSS-30017: Register Output Driving Its Own Control Signal Directly or Through Combinational Logic
2.3.6.7.8. NSS-30018: Design Contains Delay Chains
2.3.6.8.1. SGR-30020: Synchronous and Asynchronous Ports of the Same Register Driven by the Same Signal Source
2.3.6.8.2. SGR-30021: More Than One Asynchronous Port of a Register Driven by the Same Signal Source
2.3.6.8.3. SGR-30022: Clock Port and Any Other Port of a Register Driven by the Same Signal Source
インテルのみ表示可能 — GUID: mwh1409959593258
Ixiasoft
1.4.3.1. シンプル・シフト・レジスター
このセクションの例は、単純なシングルビット幅の69ビット長のシフトレジスターを示しています。
インテル® Quartus® Prime合成は、サポートされるデバイスのALTSHIFT_TAPS IPコアにレジスター( W = 1およびM = 69 )を実装し、専用のRAMブロックまたはMLABメモリーに配置されるサポートされるデバイスのRAMにマップします。レジスターの長さが69ビット未満の場合、 インテル® Quartus® Prime合成では、シフトレジスターをロジックに実装します。
Verilog HDLシングル・ビット幅、69 ビット長シフトレジスター
module shift_1x69 (clk, shift, sr_in, sr_out); input clk, shift; input sr_in; output sr_out; reg [68:0] sr; always @ (posedge clk) begin if (shift == 1'b1) begin sr[68:1] <= sr[67:0]; sr[0] <= sr_in; end end sr_out <= sr(68); endmodule
Verilog HDLシングル・ビット幅、69 ビット長シフトレジスター
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY shift_1x69 IS PORT ( clk: IN STD_LOGIC; shift: IN STD_LOGIC; sr_in: IN STD_LOGIC; sr_out: OUT STD_LOGIC ); END shift_1x69; ARCHITECTURE arch OF shift_1x69 IS TYPE sr_length IS ARRAY (68 DOWNTO 0) OF STD_LOGIC; SIGNAL sr: sr_length; BEGIN PROCESS (clk) BEGIN IF (rising_edge(clk)) THEN IF (shift = '1') THEN sr(68 DOWNTO 1) <= sr(67 DOWNTO 0); sr(0) <= sr_in; END IF; END IF; END PROCESS; sr_out <= sr(65); END arch;