インテルのみ表示可能 — GUID: vwm1513909488806
Ixiasoft
インテルのみ表示可能 — GUID: vwm1513909488806
Ixiasoft
3.3.12.1. Simulation Models for Designs Containing LPMs or IP Cores
Functional Simulation
The インテル® Quartus® Primeプロ・エディション software provides functional simulation models that allow you to perform functional/behavioral simulation on designs containing LPMs or インテル® FPGA IP cores.
Verilog HDL | VHDL | |
---|---|---|
LPM | 220model.v | 220pack.vhd 220model.vhd |
インテル® FPGA IP cores | altera_mf.v | altera_mf.vhd altera_mf_components.vhd |
Gate-level Functional Simulation
To perform gate-level functional simulation on a design, the インテル® Quartus® Primeプロ・エディション software generates output netlist files containing information about how the design was placed into device-specific architectural blocks.
Extension | |
---|---|
Verilog HDL output file | .vo |
VHDL output file | .vho |
You can perform simulations with pre-compiled model libraries by using the ModelSim* - インテル® FPGA エディション simulator included in the インテル® Quartus® Primeプロ・エディション software. You can also compile your own selection of model libraries with the Simulation Library Compiler tool in the インテル® Quartus® Primeプロ・エディション software.