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3.3.1. Project Creation
3.3.2. Design Entry
3.3.3. IP Status
3.3.4. Design Constraints
3.3.5. Synthesis
3.3.6. Design Implementation
3.3.7. Finalize Pinout
3.3.8. Viewing and Editing Design Placement
3.3.9. Static Timing Analysis
3.3.10. Generation of Device Programming Files
3.3.11. Power Analysis
3.3.12. Simulation
3.3.13. Hardware Verification
3.3.14. View Netlist
3.3.15. Design Optimization
3.3.16. Techniques to Improve Productivity
3.3.17. Cross-Probing in the インテル® Quartus® Primeプロ・エディション Software
4.2.1.2.1. Memory Mode
4.2.1.2.2. Clocking Mode
4.2.1.2.3. Write and Read Operation Triggering
4.2.1.2.4. Read-During-Write Operation at the Same Address
4.2.1.2.5. Error Correction Code (ECC)
4.2.1.2.6. Byte Enable
4.2.1.2.7. Address Clock Enable
4.2.1.2.8. Parity Bit Support
4.2.1.2.9. Memory Initialization
4.2.1.2.10. Output Synchronous Set/Reset
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3.3.2.1. HDL Editor
In the Vivado* software you create a new HDL design file using the New Source Wizard on the Project menu. To create a new HDL design file in the インテル® Quartus® Primeプロ・エディション software, click File > New, and then select the type of file you want to create.
- To assist you in creating HDL designs, the インテル® Quartus® Prime software provides design example templates for VHDL and Verilog HDL, including language constructs examples to help you get started on a design.
- The インテル® Quartus® Prime Text Editor offers syntax coloring for highlighting HDL reserved words and comments.