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3.3.1. Project Creation
3.3.2. Design Entry
3.3.3. IP Status
3.3.4. Design Constraints
3.3.5. Synthesis
3.3.6. Design Implementation
3.3.7. Finalize Pinout
3.3.8. Viewing and Editing Design Placement
3.3.9. Static Timing Analysis
3.3.10. Generation of Device Programming Files
3.3.11. Power Analysis
3.3.12. Simulation
3.3.13. Hardware Verification
3.3.14. View Netlist
3.3.15. Design Optimization
3.3.16. Techniques to Improve Productivity
3.3.17. Cross-Probing in the インテル® Quartus® Primeプロ・エディション Software
4.2.1.2.1. Memory Mode
4.2.1.2.2. Clocking Mode
4.2.1.2.3. Write and Read Operation Triggering
4.2.1.2.4. Read-During-Write Operation at the Same Address
4.2.1.2.5. Error Correction Code (ECC)
4.2.1.2.6. Byte Enable
4.2.1.2.7. Address Clock Enable
4.2.1.2.8. Parity Bit Support
4.2.1.2.9. Memory Initialization
4.2.1.2.10. Output Synchronous Set/Reset
インテルのみ表示可能 — GUID: csj1513905010837
Ixiasoft
4.1.1. Converting I/O Buffers
The インテル® Quartus® Primeプロ・エディション Compiler inserts input, output, or bidirectional buffers automatically.
To convert a design's buffers to the インテル® Quartus® Primeプロ・エディション software:
- Remove all buffer primitives from the Xilinx* design in the HDL code.
- Replace the primitives with wire or signal assignments in the HDL code.
- In the Assignment Editor, perform assignments depending on the type of buffer:
Type of Buffer Assignment to use Buffers with selectable I/O standard I/O Standard Global buffers Global Signal Global buffer with I/O Standard I/O Standard