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3.3.1. Project Creation
3.3.2. Design Entry
3.3.3. IP Status
3.3.4. Design Constraints
3.3.5. Synthesis
3.3.6. Design Implementation
3.3.7. Finalize Pinout
3.3.8. Viewing and Editing Design Placement
3.3.9. Static Timing Analysis
3.3.10. Generation of Device Programming Files
3.3.11. Power Analysis
3.3.12. Simulation
3.3.13. Hardware Verification
3.3.14. View Netlist
3.3.15. Design Optimization
3.3.16. Techniques to Improve Productivity
3.3.17. Cross-Probing in the インテル® Quartus® Primeプロ・エディション Software
4.2.1.2.1. Memory Mode
4.2.1.2.2. Clocking Mode
4.2.1.2.3. Write and Read Operation Triggering
4.2.1.2.4. Read-During-Write Operation at the Same Address
4.2.1.2.5. Error Correction Code (ECC)
4.2.1.2.6. Byte Enable
4.2.1.2.7. Address Clock Enable
4.2.1.2.8. Parity Bit Support
4.2.1.2.9. Memory Initialization
4.2.1.2.10. Output Synchronous Set/Reset
インテルのみ表示可能 — GUID: mtr1422491930353
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3.2.1.2. place_design/route_design
Depending on the use mode, the Vivado* software provides different commands to place and route device resources into the FPGA device. In Project Mode, the launch_runs impl 1 executable performs place and route, and the equivalent インテル® Quartus® Primeプロ・エディション executable is quartus_fit. In Non-Project Mode, the Vivado* software provides the place_design and route_design executables. The インテル® Quartus® Primeプロ・エディション software allows you perform place and route stages separately in the quartus_fit executable through arguments.
The インテル® Quartus® Primeプロ・エディション Fitter includes the following stages:
- Plan—places all periphery elements (such as I/Os and PLLs) and determines a legal clock plan, without core placement or routing.
- Early Place—places all core elements in an approximate location to facilitate design planning. Finalizes clock planning for インテル® Stratix® 10 designs.
- Place—places all core elements in a legal location.
- Route—creates all routing between the elements in the design.
- Retime 12 —performs register retiming and moves existing registers into Hyper-Registers to increase performance by removing retiming restrictions and eliminating critical paths.
- Finalize—for インテル® Arria® 10 and インテル® Cyclone® 10 GX devices, converts unnecessary tiles to High-Speed or Low-Power. For インテル® Stratix® 10 devices, performs post-route.
- Fast Forward12—generates detailed reports that estimate performance gains achievable by making specific RTL modifications.
You can run each Fitter stage standalone by providing the appropriate argument to the quartus_fit executable. For more information, run quartus_fit --help.
The following example performs place-and-route by fitting the logic of the インテル® Quartus® Primeプロ・エディション filtref project:
quartus_fit filtref
For command line help, type quartus_fit --help at the command prompt.
12 Retime and Fast-Forward Compilation available only for インテル® Stratix® 10 devices.