インテルのみ表示可能 — GUID: zdh1515535946185
Ixiasoft
インテルのみ表示可能 — GUID: zdh1515535946185
Ixiasoft
4.4. Setting Up the Simulation Environment
インテル® Quartus® Primeプロ・エディション software supports RTL and gate-level design simulation in the EDA simulators listed in the table. Unless you use a simulator specific to Xilinx* , the simulation environment in the インテル® Quartus® Primeプロ・エディション is similar. The Xilinx* environment also supports all the following EDA simulators:
Vendor | Simulator | Version | Platform |
---|---|---|---|
Aldec* | Active-HDL* | 10.3 | Windows* |
Aldec* | Riviera-PRO* | 2016.10 | Windows, Linux |
Cadence* | Incisive Enterprise* | 15.20 | Linux |
Mentor Graphics* | ModelSim* - インテル® FPGA エディション | 10.5c | Windows, Linux |
Mentor Graphics* | ModelSim* PE | 10.5c | Windows |
Mentor Graphics* | ModelSim* SE | 10.5c | Windows, Linux |
Mentor Graphics* | QuestaSim* | 10.5c | Windows, Linux |
Synopsys* | VCS* VCS MX |
2016,06-SP-1 | Linux |
For more information about ModelSim* - インテル® FPGA エディション Products, refer to the Altera website.
For more information about supported simulation levels, refer to the インテル® Quartus® Primeプロ・エディション Handbook Volume 3 .