インテルのみ表示可能 — GUID: mtr1422491945625
Ixiasoft
インテルのみ表示可能 — GUID: mtr1422491945625
Ixiasoft
3.3.4. Design Constraints
The Vivado* software provides GUI editors (Device/Physical/Timing windows) to create and edit design constraints. Xilinx* designs store all the constraints and attributes in Xilinx* Design Constraint (.xdc) files, including timing and device constraints. You can also edit .xdc files with a text editor.
Intel® FPGA designs use separate files for device (.qsf) and timing (.sdc) constraints, and stores timing constraints in Synopsys* Design Constraints (SDC) format. To view and edit pin assignments, device options, and logic options, use the Assignment Editor. To view and edit timing constraints, use the Text Editor in the タイミング・アナライザー GUI.
GUI Feature | Xilinx* Vivado* Software | インテル® Quartus® Primeプロ・エディション Software |
---|---|---|
Design Constraints | Device, Physical and Timing Constraints window | Assignment Editor, タイミング・アナライザー Text Editor |
Features
The table summarizes the file format and assignment types that the tools in the インテル® Quartus® Primeプロ・エディション software set.
Assignment Type | File Format | Tools to Make Assignments |
---|---|---|
Timing | SDC | タイミング・アナライザー |
I/O-related | TCL | インターフェイス・プランナー |
QSF | Pin Planner, インターフェイス・プランナー | |
Others | Assignment Editor |
With separate constraint files, you avoid searching for timing constraints among other device constraints. Additionally, you can modify the timing constraints and check for validity without recompiling. In place of the I/O Planning in the Vivado* software, インテル® Quartus® Primeプロ・エディション software offers the インターフェイス・プランナー to plan interfaces and device periphery, and the Pin Planner to edit, validate, and export pin assignments.
For equivalence between design constraints, refer to the Set Equivalent Xilinx* Design Constraints section.