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3.3.1. Project Creation
3.3.2. Design Entry
3.3.3. IP Status
3.3.4. Design Constraints
3.3.5. Synthesis
3.3.6. Design Implementation
3.3.7. Finalize Pinout
3.3.8. Viewing and Editing Design Placement
3.3.9. Static Timing Analysis
3.3.10. Generation of Device Programming Files
3.3.11. Power Analysis
3.3.12. Simulation
3.3.13. Hardware Verification
3.3.14. View Netlist
3.3.15. Design Optimization
3.3.16. Techniques to Improve Productivity
3.3.17. Cross-Probing in the インテル® Quartus® Primeプロ・エディション Software
4.2.1.2.1. Memory Mode
4.2.1.2.2. Clocking Mode
4.2.1.2.3. Write and Read Operation Triggering
4.2.1.2.4. Read-During-Write Operation at the Same Address
4.2.1.2.5. Error Correction Code (ECC)
4.2.1.2.6. Byte Enable
4.2.1.2.7. Address Clock Enable
4.2.1.2.8. Parity Bit Support
4.2.1.2.9. Memory Initialization
4.2.1.2.10. Output Synchronous Set/Reset
インテルのみ表示可能 — GUID: sej1512596624998
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3.1. Hardware and Software Tools for FPGA Design
The インテル® Quartus® Primeプロ・エディション software provides tools similar to those found in the Xilinx* Vivado* software. The following table shows Xilinx* tool suites and the Intel® FPGA tool targeting similar design needs:
Xilinx* | Intel® | Description |
---|---|---|
Vivado* HL Design Edition
|
インテル® Quartus® Primeプロ・エディション
|
Optimized to support the advanced features in next generation FPGAs and SoCs. |
ISE* Design Suite for:
|
インテル® Quartus® Primeスタンダード・エディション for:
|
Supports older generation device families.
注: Intel® recommends using newer version of インテル® Quartus® Prime for new designs.
|
Vivado* HL WebPACK Edition | インテル® Quartus® Prime Lite Edition |
|
SDAccel Environment
|
インテル® FPGA SDK for OpenCL™
|
Development environment for OpenCL |
SDSoC Environment | Intel® SoC FPGA Embedded Development Suite | Comprehensive tool suite for embedded software development on SoCs. You can code, build, debug, and optimize in single IDE. |
Software Development Kit | Nios® II Embedded Design Suite (EDS) | Comprehensive development package to develop and debug code for SoCs |
System Generator6 for DSP | DSP Builder for Intel® FPGAs 7 8 | DSP Design Tool |
Vivado* High-Level Synthesis | Intel HLS Compiler | High-Level synthesis tool that takes in untimed software code as input and generates register-transfer level code for FPGAs. |
6 To use System Generator for DSP in Vivado* , you must buy the Vivado* HL System Edition, which supports all features of the Vivado* HL Design Edition plus System Generator for DSP.