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3.3.1. Project Creation
3.3.2. Design Entry
3.3.3. IP Status
3.3.4. Design Constraints
3.3.5. Synthesis
3.3.6. Design Implementation
3.3.7. Finalize Pinout
3.3.8. Viewing and Editing Design Placement
3.3.9. Static Timing Analysis
3.3.10. Generation of Device Programming Files
3.3.11. Power Analysis
3.3.12. Simulation
3.3.13. Hardware Verification
3.3.14. View Netlist
3.3.15. Design Optimization
3.3.16. Techniques to Improve Productivity
3.3.17. Cross-Probing in the インテル® Quartus® Primeプロ・エディション Software
4.2.1.2.1. Memory Mode
4.2.1.2.2. Clocking Mode
4.2.1.2.3. Write and Read Operation Triggering
4.2.1.2.4. Read-During-Write Operation at the Same Address
4.2.1.2.5. Error Correction Code (ECC)
4.2.1.2.6. Byte Enable
4.2.1.2.7. Address Clock Enable
4.2.1.2.8. Parity Bit Support
4.2.1.2.9. Memory Initialization
4.2.1.2.10. Output Synchronous Set/Reset
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3.3.2.4. IP Catalog and Parameter Editor
Use the IP Catalog to generate Intel® FPGA equivalents for Xilinx* primitives and IP Catalog cores. To display the IP Catalog in the インテル® Quartus® Primeプロ・エディション software, click View > IP Catalog.
Features of the IP Catalog
- Allows you to create custom IP cores that are optimized for the design's target device.
- Intel® provides a library-of parameterized-modules (LPM). This library offers architecture-independent functions for all devices that the インテル® Quartus® Primeプロ・エディション supports.
- The IP Catalog is also available from プラットフォーム・デザイナー. The プラットフォーム・デザイナー IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IPs that are available only if you access the IP Catalog from プラットフォーム・デザイナー. To open プラットフォーム・デザイナー from the インテル® Quartus® Primeプロ・エディション software, click Tools > プラットフォーム・デザイナー . To display the IP Catalog from プラットフォーム・デザイナー, click View > IP Catalog.