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3.3.1. Project Creation
3.3.2. Design Entry
3.3.3. IP Status
3.3.4. Design Constraints
3.3.5. Synthesis
3.3.6. Design Implementation
3.3.7. Finalize Pinout
3.3.8. Viewing and Editing Design Placement
3.3.9. Static Timing Analysis
3.3.10. Generation of Device Programming Files
3.3.11. Power Analysis
3.3.12. Simulation
3.3.13. Hardware Verification
3.3.14. View Netlist
3.3.15. Design Optimization
3.3.16. Techniques to Improve Productivity
3.3.17. Cross-Probing in the インテル® Quartus® Primeプロ・エディション Software
4.2.1.2.1. Memory Mode
4.2.1.2.2. Clocking Mode
4.2.1.2.3. Write and Read Operation Triggering
4.2.1.2.4. Read-During-Write Operation at the Same Address
4.2.1.2.5. Error Correction Code (ECC)
4.2.1.2.6. Byte Enable
4.2.1.2.7. Address Clock Enable
4.2.1.2.8. Parity Bit Support
4.2.1.2.9. Memory Initialization
4.2.1.2.10. Output Synchronous Set/Reset
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4.2.1.3. Determining Memory Block and Mapping Ports
- If you are not sure which memory block to select, or are not particular about the memory block type, select AUTO in the IP Catalog/Parameter Editor.
This option allows the インテル® Quartus® Prime software to determine the memory block type at compile time.
- To find the type of memory block that the インテル® Quartus® Prime software assigned to your design, check the インテル® Quartus® Prime Fitter RAM Summary Report.
- Otherwise, build the memory blocks in the IP Catalog/Parameter Editor using the proper plug-in.
The available plug-ins are:
表 45. Memory Modes/Functions and Related Plug-In Memory Modes/Function Plug-In Single-port RAM RAM:1-PORT Simple dual-port RAM RAM:2-PORT True dual-port RAM RAM:2-PORT Simple quad-port RAM ( インテル® Stratix® 10 only) RAM:4-PORT Single-port ROM ROM:1-PORT Dual-port ROM ROM:2-PORT For information about memory options, and how to build the memory function through the IP Catalog/Parameter Editor, refer to the embedded memory user guide.
- Identify the port-mapping from Xilinx* memory ports to Intel® FPGA memory ports.