インテルのみ表示可能 — GUID: mxh1621901926264
Ixiasoft
インテルのみ表示可能 — GUID: mxh1621901926264
Ixiasoft
4.6. バーストAvalon-MM Slave (BAS) インターフェイース
信号名 | I/Oタイプ | 説明 |
---|---|---|
bas_vfactive_i | Input | アサートされると、これらの信号は、受信したTLPが仮想機能をターゲットにしていることを示します。 |
H-Tile: bas_pfnum_i[1:0] P-Tile and F-Tile and R-Tile: bas_pfnum_i[2:0] |
Input | Specifies a target PF number |
[10..0] | Input | Specifies a target VF number |
H-Tile: bas_address_i [63:0] P-Tile, F-Tile and R-Tile : bas_address_i[<n>-1:0] |
Input | Specify the byte address regardless of the data width of the master. The Bursting Slave's addresses must be aligned to the width of the data bus. For example, if the data width is 64B, the addresses must align to 64B. In P/F/R-Tile End Point mode the BAS address width <n> is always 64. In P/F/R-Tile Root Port mode, if ATT is enabled then <n> : (ATT Table Address Width) + (ATT Window Address Width), else <n> : 64 |
x16 [63:0] x8/x4 (256-bit): bas_byteenable_i[31:0] x4 (128-bit): bas_byteenable_i[15:0] |
Input | Enables one or more specific bytes of write data during transfers on interfaces. For x16, each bas_byteenable bit corresponds to a byte in bas_writedata_i[511:0]. For single-cycle read bursts and for all write bursts, all contiguous sets of enabled bytes are supported. For burst read transactions, the bas_byteenable_i[63:0] must be 64'hFFFF_FFFF_FFFF_FF |
x16 [3:0] x8/x4 (256-bit): bas_burstcount_i[4:0] x4 (128-bit): bas_burstcount_i[5:0] |
Input | Used by a bursting master to indicate the number of transfers in each burst. |
bas_read_i | Input | Asserted to indicate a read transfer. |
x16 [511:0] x8/x4 (256-bit): bas_readdata_o[255:0] x4 (128-bit): bas_readdata_o[127:0] |
Output | Read data to the user logic in response to a read transfer |
bas_readdatavalid_o | Output | When asserted, indicates that the readdata signal contains valid data. For a read burst with burstcount value <n>, the readdatavalid signal must be asserted <n> times, once for each readdata item. |
bas_write_i | Input | Asserted to indicate a write transfer |
x16 [511:0] x8/x4(256-bit): bas_writedata_i[255:0] x4 (128-bit): bas_writedata_i[127:0] |
Input | 書き込み転送用の32ビットデータ。 |
bas_waitrequest_o | Output | アサートされると、この信号はMMコアが要求に応答する準備ができていないことを示します。 waitrequestAllowance = 0 The master cannot issue any transfer after bas_waitrequest_o is asserted. |
[1..0] | Output |
Carries the response status:
|