| 更新対象: |
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| インテル® アクセラレーション・スタック (インテル® Xeon® CPU & FPGA対応) 1.2 |
| この翻訳版は参照用であり、翻訳版と英語版の内容に相違がある場合は、英語版が優先されるものとします。翻訳版は、資料によっては英語版の更新に対応していない場合があります。最新情報につきまし ては、必ず英語版の最新資料をご確認ください。 |
The ASE provides a transactional model for the Core Cache Interface protocol and a memory model for the FPGA-attached local memory. The local memory model provides a simulation model for the dual-memory banks on the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA.
The ASE also validates Accelerator Functional Unit (AFU) compliance to the following protocols and APIs:
This document describes how to simulate a sample AFU using the ASE environment. Refer to the Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) User Guide 1.1 for comprehensive details on ASE capabilities and internal architecture.
Intel®Accelerator Functional Unit (AFU) Simulation Environment (ASE)
Quick Start User Guide .| Term | Abbreviation | Description |
|---|---|---|
| Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs | Acceleration Stack | A collection of software, firmware and tools that provides performance-optimized connectivity between an Intel® FPGA and an Intel® Xeon® processor. |
| Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA | Intel® PAC with Intel® Arria® 10 GX FPGA | PCIe* accelerator card with an Intel® Arria® 10 FPGA. Contains an FPGA Interface Manager (FIM) that pairs with an Intel® Xeon® processor over PCIe* bus. |
| Intel® Xeon® Scalable Platform with Integrated FPGA | Integrated FPGA Platform | Intel® Xeon® plus FPGA platform with the Intel® Xeon® and an FPGA in a single package and sharing a coherent cache of memory via Ultra Path Interconnect (UPI). |