JPEG-D-S: Baseline JPEG Decoder
このオファーについて
This JPEG-D-S core is a high-performance JPEG decoder supporting the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard. It is suitable for decompressing JPEG images and the video payload of Motion-JPEG container formats.. The core decodes one color sample per clock cycle, and is able to process Full-HD 1080p video in most FPGA devices. Once programmed, the easy-to-use decoder operates on a standalone basis, parsing marker segments and decompressing coded data with no assistance from a host processor. SoC integration is straightforward thanks to standardized AMBA' interfaces: AXI Streaming for pixel and decompressed data, and a 32-bit APB slave interface for registers access. FEATURES: Area-efficient, high-performance Baseline JPEG decoder for ASIC and FPGA Standards Support ISO/IEC 10918-1 Standard Baseline Decoder Single-frame JPEG images and Motion JPEG payloads Up to four color components 8-bit color samples All widely used color subsampling formats, and any image size up to 64k x 64k All scan configurations and all JPEG formats All marker segments expect DNL Up to four Huffman Tables Up to four 8-bit or 16-bit Quantization tables Interfaces AXI Streaming I/O data interfaces APB Control/Status interface Optional AHB wrapper with DMA capabilities Performance and Size One decoded sample per clock cycle Small silicon footprint (65k Gates) Ease of Integration Requires no programming or control from host Reports image format Detects and reports marker syntax errors Delivered with bit-accurate software model Optional Block-to-Raster Conversion with AXI or standard memory interface towards the lines buffer Format Available as a netlist for ASICs or FPGAs
技術仕様
- カテゴリー:
- ソフトウェアと IP コア: FPGA 知的財産コア: DSP: ビデオ画像処理
- エンドカスタマーのタイプ:
-
中小規模のビジネス
その他
エンタープライズ
インテルのテクノロジーを含む
Cyclone® V FPGA & SoC FPGA
Stratix® V FPGA
インテル® Arria® 10 FPGA & SoC FPGA
インテル® MAX® 10 FPGA
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Jpeg-d-s: Baseline Jpeg Decoder
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