PCI-M32: 32-bit, 33 MHz PCI Master/Target
このオファーについて
The main PCI-M32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the user instead focus on the application development. The PCI-M32 Interface supports 32-bit address/data bus and operates up to 33 MHz (66 MHz optional) PCI clock frequency. It is fully compliant with the PCI Local Bus Specification, Revision 2.3. The PCI-M32 Interface has both Master and Target capabilities. The interface implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required. The Target part supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 2 GB. Both Target and Master supported commands are: - Configuration Read, Configuration Write - Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL) - I/O Read, I/O Write
技術仕様
- カテゴリー:
- ソフトウェアと IP コア: FPGA 知的財産コア: インターフェイス・プロトコル: PCI
- エンドカスタマーのタイプ:
-
中小規模のビジネス
その他
エンタープライズ
リソース
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Arria® V FPGA & SoC FPGA
Stratix® IV FPGA
Excalibur™
Cyclone® IV FPGA
APEX™
Cyclone® V FPGA & SoC FPGA
Stratix® III FPGA
Cyclone® III FPGA
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Pci-m32: 32-bit, 33 Mhz Pci Master/target
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