L8051XC1: Legacy-Configurable 8051-Compatible Microcontroller IP Core
このオファーについて
The L8051XC1 core implements an MCS 51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU based systems. The core can be configured to execute an instruction every 12, 6, or 4 clock cycles. Architectural extensions are user-selectable, including multiple data-pointers, a multiply-division unit, and a power management unit. Furthermore, the 8051 CPU can be coupled with a wide range of peripherals matching the behavior and timing of peripherals found in legacy architectures from various vendors. Several pre-configured versions are offered; custom variations are also available.
技術仕様
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- ソフトウェアと IP コア: FPGA 知的財産コア: プロセッサーと周辺機器: 組込み機器向けプロセッサー
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L8051xc1: Legacy-configurable 8051-compatible Microcontroller Ip Core
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