Cyclone® II デバイス・ハンドブック、第 1 巻、第 12章: Cyclone II デバイスのエンベデッド乗算器

This document provides information of configuration and testing of Cyclone® II devices.

This chapter discusses DC Characteristics and Timing Specifications. Unless otherwise noted, the parameter values in this chapter apply to all Cyclone® II devices. AC and DC characteristics are specified using the same numbers for both commercial and indu

This document provides information on Cyclone® II M4K ram and interfacing with external memory.

This chapter describes the ordering codes for Cyclone® II devices.

This chapter focuses on the implementations of a double data rate I/O interface using the hardware features available in Cyclone® II devices and explains briefly how each memory standars uses the Cyclone II features.

This chapter provides information on the Cyclone® II device architecture.

This chapter discusses how to use the IEEE Std. 1149.1 BST circuitry in Cyclone® II devices.

This chapter provides package information for Cyclone® II devices, including: device and package cross reference, thermal resistance values, and package outline.

This chapter is a guide to understanding the input and output capabilities of the Cyclone® II devices.

This chapter discusses the Cyclone® II device family features, Cyclone II device package offerings and maximum user I/O pins.

This chapter discusses the electro-static dischage (ESD) protection and the power-on reset (POR) circuitry in Cyclone® II devices. The POR circuitry keeps the devices in the reset state until the Vcc is within operating range.

This chapter describes how to use Cyclone® II I/O pins for differential signaling.