VHDL: Unsigned Multiplier with Registered I/O

author-image

投稿者:

This example describes an 8-bit unsigned multiplier design with registered I/O in VHDL.

Figure 1. Unsigned multiplier top-level diagram.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.