This example describes an 8-bit unsigned multiplier-accumulator design with registered I/O ports and synchronous load in Verilog HDL. Synthesis tools are able to detect multiplier-accumulator designs in the HDL code and automatically infer the altmult_accum megafunction to provide optimal results.
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Table 1. Unsigned Multiplier-Accumulator Port Listing
| Port Name | Type | Description |
|---|---|---|
dataa[7:0], datab[7:0] |
Input | 8-bit data inputs |
| clk | Input | Clock input |
| aclr | Input | Asynchronous clear input |
| clken | Input | Clock enable input |
| sload | Input | Synchronous load input |
| adder_out[15:0] | Output | 16-bit data output |