Verilog HDL: Single Clock Synchronous RAM



This example describes a 64-bit x 8-bit single clock synchronous RAM design with different read and write addresses in Verilog HDL. Synthesis tools are able to detect single clock synchronous RAM designs in the HDL code and automatically infer either the altsyncram or altdpram megafunctions, depending on the architecture of the target device.

Figure 1. Single Clock synchronous RAM top-level diagram.

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