Board Update Portal Based on Nios® II Processor with EPCQ

Recommended For:

  • Device: Cyclone® V

  • Quartus®: v15.1

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This design example is a web-server based Board Update Portal (BUP) design, which contains a Nios II processor and an Intel® FPGA IP for Triple Speed Ethernet Media Access Control (MAC). The design example implements basic remote configuration features in Nios II-based systems with EPCQ for Cyclone® V E FPGA device.

The design can obtain an IP address from any DHCP server and serve a web page from the flash on the board to any host computer on the same network. The web page allows you to upload new FPGA designs for both user hardware and user software, at the same time you can also trigger reconfiguration from factory image to user image through the web page.

Using This Design Example

This design runs on Cyclone V E FPGA development kit. To run this example, download the installation package from Intel FPGA design store. Follow the instructions in the reference guide to run the design.

If you failed to run the design example, refer to the FTA to debug and find the possible root cause. If you would like to migrate the design to other development kits, refer to the design migration guideline for details.

Design Specifications

The design contains the following components:

  • Altera® Serial Flash Controller
  • Altera Phase-Locked Loop (PLL)
  • Altera Remote Update
  • JTAG UART
  • Nios II Gen2 Processor
  • On-Chip Memory (RAM or ROM)
  • PIO (Parallel I/O)
  • Reset Controller
  • Scatter-Gather DMA Controller
  • System ID Peripheral
  • Triple-Speed Ethernet

Block Diagram