How do I change the data rate and transceiver reference clock frequency for an Example Design generated for the Interlaken Intel® FPGA IP targeting the Intel® Stratix® 10 to a value slightly different than what is selected in the IP Paramet...

The Interlaken (2nd Generation) Intel® FPGA IP targetting the Intel® Stratix® 10 H-Tile or E-Tile only supports a select number of data rate and reference clock options in the IP Parameter Editor GUI.

In order to work around this issue, you should perform the following steps to vary the data rate and transceiver reference clock frequency to a slightly different value once the Interlaken (2nd Generation) Intel® FPGA IP Example Design targetting the Intel® Stratix® 10 H-Tile or E-Tile has been generated.

Steps to change the data rate/reference clock frequency when targeting Intel® Stratix® 10 E-Tile:

• Add the following line to /uflex_ilk_0_example_design/example_design/quartus/example_design.sdc

create_clock -name pll_ref_clk -period " MHz" [get_ports pll_ref_clk]

• Change the following settings in /uflex_ilk_0_example_design/ilk_uflex/altera_xcvr_native_s10_etile_2101/synth/ilk_uflex_ip_parameters_.tcl

[Line 12] dict set native_phy_ip_params pma_tx_data_rate_profile0 ""

[Line 13] dict set native_phy_ip_params pma_rx_data_rate_profile0 ""

[Line 28] dict set native_phy_ip_params pma_tx_pll_refclk_freq_mhz_profile0 ""

[Line 30] dict set native_phy_ip_params pma_rx_pll_refclk_freq_mhz_profile0 ""

Steps to change the data rate/reference clock frequency when targeting Intel® Stratix® 10 H-Tile:

• Add the following line to  /uflex_ilk_0_example_design/example_design/quartus/example_design.sdc

create_clock -name pll_ref_clk -period " MHz" [get_ports pll_ref_clk]

• /uflex_ilk_0_example_design/ilk_uflex/altera_xcvr_native_s10_htile_1921/synth/ilk_uflex_ip_parameters_.tclで次の設定を変更します。

[Line 13] dict set native_phy_ip_params set_data_rate_profile0 ""