In SOPC Builder, failure to assign an Arbitration Priority of 1 to an Avalon-MM interface can result in unpredictable behavior

Some configurations synchronous resets are not supported by SOPC Builder. If any of the following conditions are met, the HDL that SOPC Builder generates fails to connect reset ports:

• リセットポートがクロックに関連付けられていない。
• The reset port is an output and no Avalon interface (master or slave) exists on the same clock domain.
• The reset port is an input and its associated clock is an output.

No validation or generation messages are displayed.

リセットポートが接続されていないことを確認するには、次の手順を実行します。

1. Open the top-level design file generated by SOPC Builder in a text editor. (The top-level design file has a file name equal to the system name and a file extension corresponding to the HDL language you chose for system generation.)
2. Inspect the instantiation of each module. For a given module named X in the SOPC Builder system, a module/entity named X is instantiated in the top-level design file. In the module/entity instantiation, the ports are connected by name. If any of the conditions listed in the Issue description are met, the reset signal is not connected to the global reset bus.

未接続のリセットポートが見つかる場合は、次のいずれかの操作を行います。

1. Use the Qsys Editor. On the Tools menu of the main Quartus II window, click Qsys and then open the SOPC Builder Design File (.sopc) and convert your system to Qsys.
2. Manually modify the HDL to connect the reset. If the reset is expected to be synchronized, you must also manually implement synchronization. Reset synchronizers have a module name that consists of _reset__domain_synch_module. For example, an SOPC system named sys with a clock source named clk_0 has a reset synchronizer module named sys_reset_clk_0_domain_synch_module.

A reset synchronizer, for example, is generated for an external clock source in your SOPC system.