一部のサードパーティー製シミュレーション・ツールではメモリー初期化ファイル (.mif) 形式がサポートされていません。回避策は以下の通りです。
まず、.mif を 16 進数 (インテル形式) に変換します。..
次に、HDL コードを変更してメモリーファイル名の参照を変更します。
altsyncram altsyncram_component (
.clock0 (inclock)
.wren_a (wren_a)
.address_b (address_b)
.clock1 (アウトクロック)
.data_b (data_b)
.wren_b (wren_b)
.address_a (address_a)
.data_a (data_a)
.q_a (sub_wire0)
.q_b (sub_wire1)
.aclr0 (1\'b0)
.aclr1 (1\'b0)
.addressstall_a (1\b0)
.addressstall_b (1\b0)
.byteena_a (1\b1)
.byteena_b (1\b1)
.clocken0 (1\'b1)
.clocken1 (1\'b1)
.clocken2 (1\'b1)
.clocken3 (1\'b1)
.ecc彼方 ()
.rden_a (1\b1)
.rden_b (1\'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0"、
altsyncram_component.clock_enable_input_a = "BYPASS"、
altsyncram_component.clock_enable_input_b = "BYPASS"、
altsyncram_component.clock_enable_output_a = "BYPASS"、
altsyncram_component.clock_enable_output_b = "BYPASS"、
altsyncram_component.indata_reg_b = "CLOCK0"、
altsyncram_component.init_file = "test.mif"、
altsyncram_component.intended_device_family = "Cyclone IV GX"、
altsyncram_component.lpm_type = "altsyncram"、
altsyncram_component.num num num_a = 32、
altsyncram_component.num num num_b = 32、
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT"、
altsyncram_component.outdata_aclr_a = "NONE"、
altsyncram_component.outdata_aclr_b = "NONE"、
altsyncram_component.outdata_reg_a = "CLOCK1"、
altsyncram_component.outdata_reg_b = "CLOCK1"、
altsyncram_component.power_up_uninitialized = "FALSE"、
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA"、
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA"、
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA"、
altsyncram_component.widthad_a = 5
altsyncram_component.widthad_b = 5
altsyncram_component.width_a = 8
altsyncram_component.width_b = 8
altsyncram_component.width_byteena_a = 1、
altsyncram_component.width_byteena_b = 1、
altsyncram_component.wrdress_wraddress_reg_b = "CLOCK0";
宛先
altsyncram altsyncram_component (
.clock0 (inclock)
.wren_a (wren_a)
.address_b (address_b)
.clock1 (アウトクロック)
.data_b (data_b)
.wren_b (wren_b)
.address_a (address_a)
.data_a (data_a)
.q_a (sub_wire0)
.q_b (sub_wire1)
.aclr0 (1\'b0)
.aclr1 (1\'b0)
.addressstall_a (1\b0)
.addressstall_b (1\b0)
.byteena_a (1\b1)
.byteena_b (1\b1)
.clocken0 (1\'b1)
.clocken1 (1\'b1)
.clocken2 (1\'b1)
.clocken3 (1\'b1)
.ecc彼方 ()
.rden_a (1\b1)
.rden_b (1\'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0"、
altsyncram_component.clock_enable_input_a = "BYPASS"、
altsyncram_component.clock_enable_input_b = "BYPASS"、
altsyncram_component.clock_enable_output_a = "BYPASS"、
altsyncram_component.clock_enable_output_b = "BYPASS"、
altsyncram_component.indata_reg_b = "CLOCK0"、
altsyncram_component.init_file = "test.mmc"、
altsyncram_component.intended_device_family = "Cyclone IV GX"、
altsyncram_component.lpm_type = "altsyncram"、
altsyncram_component.num num num_a = 32、
altsyncram_component.num num num_b = 32、
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT"、
altsyncram_component.outdata_aclr_a = "NONE"、
altsyncram_component.outdata_aclr_b = "NONE"、
altsyncram_component.outdata_reg_a = "CLOCK1"、
altsyncram_component.outdata_reg_b = "CLOCK1"、
altsyncram_component.power_up_uninitialized = "FALSE"、
altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA"、
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA"、
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA"、
altsyncram_component.widthad_a = 5
altsyncram_component.widthad_b = 5
altsyncram_component.width_a = 8
altsyncram_component.width_b = 8
altsyncram_component.width_byteena_a = 1、
altsyncram_component.width_byteena_b = 1、
altsyncram_component.wr customization_wraddress_reg_b = "CLOCK0";