Free Academic Software

Digital logic courses use the Intel® Quartus® Prime Lite Edition software, and also the ModelSim*-Intel FPGA Starter Edition software. Computer organization courses use the Intel Quartus Prime Lite Edition software and also the Monitor Program. Embedded systems courses use the Embedded Linux, the Intel FPGA SDK for OpenCL™, and the Intel HLS Compiler. To learn more, read the sections below.

The Intel® Quartus® Prime software is a complete CAD system for designing digital circuits. For use in teaching, the FPGA University Program recommends the Intel Quartus Prime Lite Edition software, which does not require a license. The licensed commercial version of the Intel Quartus Prime Standard and Pro Edition software is available for installation in university laboratory facilities.

To download the Intel Quartus Prime software, click here. To determine the appropriate version of the Intel Quartus Prime software for the device on your board, use the "Select by Device" tab on the download page or check the Device Support List here.

The Intel® Quartus® Prime software comes with a Vector Waveform Editor tool to allow users to draw the test input signals for simulation and select which signal should be shown in the simulation results. The method of running the Waveform Editor tool has varied over the various releases of the Intel Quartus Prime software. A brief discription of the Waveform Editor tool with regards to different versions of the Intel Quartus Prime software is given below. For more information, please see the FPGA University Program tutorial "Introduction to Quartus Simulation".


Starting with the Intel Quartus Prime software v13.0, the Waveform Editor tool for performing simulations can be opened from within the Intel Quartus Prime software. This is accomplished by selecting “File -> New -> University Program VWF”. Test vectors created with this tool can be used in simulation of your circuits by running the ModelSim*-Intel FPGA simulation tool. The simulator can be started from within the Waveform Editor, or by using the NativeLink flow.


For Intel Quartus Prime software v10.1 through 12.1, the Waveform Editor tool could be used only to enter test inputs and set output signals to view. Running simulations was done using a separate tool, Qsim. For Intel Quartus Prime software v10.1 and 11.0, the QSim tool and Waveform Editor must be installed separately by using the FPGA University Program Installer. Beginning with the Intel Quartus Prime software v11.1, the QSim tool and Waveform Editor are bundled with the Intel Quartus Prime software. The QSim tool can be invoked from a command window by using the command "quartus_sh --qsim". The quartus_sh executable is part of the Intel Quartus Prime software. It can be found in the folder where the Intel Quartus Prime software is installed, for example C:\altera\12.0\quartus\bin. For this example of an installation folder you would type the command C:\altera\12.0\quartus\bin\quartus_sh --qsim. Note that if you are using the Intel Quartus Prime Standard Edition software and you are running a 64 bit operating system, then the executable is found in quartus\bin64\.


For Intel Quartus Prime software v9.1 and earlier, the Waveform Editor tool was included with the Intel Quartus Prime software and used the internal Intel Quartus software simulator.


ModelSim*-Intel® FPGA software is a widely-used logic simulation tool for verification and debugging of digital circuits. Intel provides a version of the ModelSim-Intel FPGA software, which includes libraries for Intel's FPGAs. You can download the ModelSim-Intel FPGA software program along with the Intel Quartus® Prime software.

The Platform Designer is used for designing and implementing embedded computer systems. It facilitates the creation of embedded systems that include processors, memory interfaces, and a variety of I/O devices. The Platform Designer is included as a part of the Intel® Quartus® Prime software.

The Monitor Program allows students to easily compile and debug both assembly language and C programs. It supports both the Arm* Cortex*-A9 and Nios® II processors. The Monitor Program includes standard debugging features, such as single-step, breakpoints, register and memory display, and so on.

This software is available as part of the FPGA University Program Installer. The suite also contains the FPGA University Program intellectual property (IP) cores and computer systems examples.

The University Program Installer contains the Monitor Program and computer systems examples. Depending on the selected version, the installer additionally contains the Intel® FPGA University Program IP cores or their patches (see the University Program IP Core section above for more details).

We provide SD card images containing an Ubuntu-based Linux* distribution for use with our SoC-based DE-series boards. The Linux distribution can be used for embedded Linux exercises and projects. Features include:

  • Command line interface through serial UART or SSH
  • Desktop interface through VNC connection
  • Command line FPGA programming capability
  • Automatic FPGA programming at boot up, using the default computer system for the board (the same system that is included with the Intel® FPGA Monitor Program)
  • Built-in GCC toolchain for compiling code natively on the board
  • Sample applications that demonstrate FPGA communication and driver development
  • OpenCL™ support for our boards that have the OpenCL board support package (BSP)

To get started, refer to the tutorial Using Linux on the DE1-SoC and download the appropriate SD card image from the list in the table below.

The Intel® FPGA SDK for Open Computing Language (OpenCL™) allows a user to abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow. Emulate your OpenCL C accelerator code on an x86-based host in seconds, get a detailed optimization report with specific algorithm pipeline dependency information, pushing the longer compile time to the end when you are pleased with your kernel code results. Leverage prewritten optimized OpenCL or register transfer level (RTL) functions, calling them from the host or directly from within your OpenCL kernels.

Intel® HLS Compiler accelerates FPGA design by enabling hardware developers to work at higher levels of abstraction using untimed C/C++. Simulation times for abstract models developed in C/C++ typically finish in seconds vs register transfer level (RTL) simulations that can take minutes or hours. Intel HLS Compiler generates production quality RTL that is device optimized for Intel FPGAs.

DSP Builder for Intel® FPGAs is a tool for designing systems for digital signal processing (DSP). It contains a library of modules that can be used in the industry-standard MathWorks*/Simulink tools. The DSP Builder for Intel FPGAs is available free of charge for universities.