Intel® FPGA E-Tile Transceiver Basics (OS101116)

59 Minutes Online Course

Course Description

Intel® Agilex™ F-Series and Intel Stratix® 10 TX, MX and DX FPGAs contain different embedded transceivers types to support the wide range of I/O bandwidth requirements of today’s high-performance systems. This training is the first step in learning how to build a high-speed interface using E-tiles, whether your target application requires Ethernet, FibreChannel, Common Public Radio Interface (CPRI) or even your own proprietary, non-standard protocol. By the end of this training, you will be able to define the blocks found in the E-tile transceivers and how the blocks are used together to ensure successful data transfers between high-speed serial links and your FPGA core logic. You will also be introduced to a tool to help plan your use of E-tile channels called the Intel Stratix 10 FPGA

At Course Completion

You will be able to:

  • Describe the blocks found in the transmitter and receiver paths of Intel Agilex F-Series and Intel Stratix 10 FPGA E-tile high-speed serial transceivers
  • Describe how each transceiver block is used in supporting a high-speed serial interface
  • Select the appropriate channel configuration for your design based on your high-speed protocol requirements
  • Use the Intel Stratix 10 FPGA E-tile Channel Placement Tool to create a valid layout of transceiver channels for your design project

Skills Required

  • Background in digital logic
  • General understanding of FPGA architecture

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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