Intel® Stratix® 10 FPGA L- and H-Tile Transceiver Basics (OS101115)

Course Description

Intel® FPGAs contain embedded transceivers that support the wide range of I/O bandwidth requirements of systems using high-performance FPGAs. This online course provides an overview of the transceivers found on the Intel Stratix® 10 family members with L- and H-tiles.

This training is the first step in learning how to build a high-performance interface, particularly if your interface needs are more customized, or non-standard. By the end of this training, you will be able to define the blocks found in the transmitter and receiver data paths as well as how the blocks are used to ensure successful data transfers across high-speed serial links.

Note this training also applies to select Intel Agilex™ family members with H-tiles.

At Course Completion

You will be able to:

• Describe the blocks found in the transmitter and receiver paths of Intel Stratix 10 FPGA L
• and H-tile high-speed serial transceivers
• Describe how each transceiver block is used in supporting a high-speed serial interface

Skills Required

• Background in digital logic
• General understanding of FPGA architecture

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Advanced Optimization with Intel® Hyperflex™ Architecture
• Introduction to the 10Gb Ethernet PHY Intel® FPGA IP Cores
• Introduction to the Low Latency 10Gb Ethernet MAC Intel® FPGA IP Core
• Introduction to the Triple-Speed Ethernet MegaCore Function
• Performance Optimization with Intel® Hyperflex™ Architecture
• Stratix® 10 HyperFlex™ Architecture Overview

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• I/O Interfaces

Class Schedule

Result Showing 1