Introduction to the Arria 10 Hard IP for PCI Express (OPCIINTROG10)

Course Description

Are you new to using the Hard IP for PCI Express® found in Arria® 10 devices? If so, then you should start with this course. In this class, you will learn the capabilities and features of the Hard IP for PCI Express to see why it is the right solution for your PCI Express design. You will learn the core variations that are available to help you decide which variation is the best based on your design requirements.

While this course current focuses on the Arria 10 FPGA family, the Stratix® 10 family will be added in a future update to this course.

At Course Completion

You will be able to:

• Describe the basic and advanced features of the Hard IP for PCI Express block found in select Altera® Arria10 FPGAs
• Select between the different Hard IP for PCI Express core variations based on use model and required features

Skills Required

• Some understanding of the PCI Express Protocol specification is helpful, but not required
• Familiarity with common high-speed transceiver architecture OR viewing the following Transceiver Basics course OR attending the Building Gigabit Interfaces in Generation 10 Transceiver Devices
• Familiarity with FPGA/CPLD design flow
• Familiarity with the Quartus® II design software

Prerequisites

We recommend completing the following courses:

• Building Interfaces with Arria 10 High-Speed Transceivers
• The Intel® Quartus® Prime Software: Foundation (Instructor-led / Virtual Training)
• The Intel® Quartus® Prime Software: Foundation (Standard Edition) (Online Training)
• Transceiver Basics for 20 nm and 28 nm Devices
• Using the Intel® Quartus® Prime Standard Edition Software: An Introduction

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• Customizing Intel® Stratix® 10, Intel Arria® 10 & Intel Cyclone® 10 GX FPGA Hard IP for PCI Express*

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

• I/O Interfaces

Class Schedule

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