Intel® FPGA E-Tile Clocking (OETILECLK)

28 Minutes Online Course

Course Description

This online course will introduce the clocking resources found in Intel® Agilex™ F-Series and Intel Stratix® 10 MX/TX/DX FPGA E-Tiles. In this course, you will learn about the reference clocks available on the E-tile. Then, you will learn how the E-tile transceiver datapath clocks are generated and distributed. Finally, you will learn how the E-tile transceiver clocks must be connected at the FPGA fabric interface. The goal of the course is to help you understand your use of clocking resources, which can be key to a successful design implementation.

At Course Completion

You will be able to:

  • Describe the clock resources of the Intel® Agilex™ F-Series and Intel Stratix® 10 FPGA MX/TX/DX E-Tiles
  • Correctly connect the FPGA interface clocks to the E-tile to avoid compilation and timing errors

Skills Required

  • Understanding of the Ethernet protocols, particularly 10G, 25G and 100G Ethernet
  • Familiarity with FPGA/CPLD design flow
  • Familiarity with the Intel Quartus Prime design software
  • Familiarity with Intel® FPGA E-Tile architecture OR viewing the following course: "Intel® FPGA E-Tile Transceiver Basics"

Prerequisites

We recommend completing the following courses:

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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