High-Level Synthesis with Intel® FPGAs (16 Hours Course) (IHLS2DAY)

16 Hours Instructor-Led / Virtual Class Course

Course Description

In the class, you will learn how to use the Intel® HLS Compiler to synthesize, optimize, and verify design IP for Intel FPGAs. We will first discuss the benefits of HLS then talk about features of the Intel HLS Compiler. You will learn how to use the compiler options, the generated reports, and the final generated files to integrate the IP within an Intel Quartus® project. Lastly you will learn how to effectively optimize your IP using the generated reports.

At Course Completion

You will be able to:

  • Use the Intel HLS Compiler to synthesize an Intel Quartus®-compatible IP
  • View Intel HLS Compiler generated reports to debug & optimize your IP
  • Co-simulate your HLS IP using an RTL simulator with a software testbench
  • Integrate the HLS-generated IP within an FPGA design
  • Use Pragmas to control HLS compilation
  • Effectively pipeline loops
  • Optimize Local Memory Architecture
  • Effectively use various data types & math support features available
  • Understand the limitations of the compiler

Skills Required

  • Basic understanding of the C programming language
  • Basic understanding of FPGAs and the Intel Quartus Development Environment

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

Result Showing 6

Virtual Classroom11/28/2017 - 11/30/2017$1390Register Now
Virtual Classroom01/09/2018 - 01/11/2018$1390Register Now
Virtual Classroom02/13/2018 - 02/15/2018$1390Register Now
Virtual Classroom03/27/2018 - 03/29/2018$1390Register Now
Virtual Classroom05/01/2018 - 05/03/2018$1390Register Now
Virtual Classroom06/12/2018 - 06/14/2018$1390Register Now