Qsys Tutorial Design Example

The Qsys System Design Tutorial (PDF) provides step-by-step instructions to create and verify a design with the Qsys system integration tool in the Quartus® II software. This design example includes the system components to design a memory tester system by following the procedures in the tutorial.

In the tutorial, you perform the following steps:

  • Create a memory tester design using components in Qsys
  • Build the design with hierarchical levels of subsystems
  • Program the FPGA and calculate the memory efficiency reported by the tester
  • Use bus functional models (BFMs) to validate one of the design components in simulation
  • Use system console to control the system using a JTAG to Avalon® Memory-Mapped (Avalon-MM) bridge

The design is scalable to test any Avalon-MM slave interface capable of read and write accesses, so you can use this design example as a starting point to test many other memory types and interfaces.

Software and Hardware Requirements

This design requires the Altera® Complete Design Suite v12.0 or later, including the following:

  • Quartus II software
  • Nios® II Embedded Design Suite
  • Modelsim®-Altera Edition or Starter Edition software

This design example is used with any of the following development boards:

The design example README file includes instructions on how to port this design to your own custom board that meets the following board requirements:

  • Altera Stratix, Cyclone, or Arria series FPGA
    • 12K logic elements (LEs) or adaptive lookup tables (ALUTs) available
    • 128k memory bits available
  • JTAG programming cable connection
  • External memory to test and memory controller with Avalon-MM slave interface

Using This Design Example

The design example is based on the systems constructed in the Qsys System Design Tutorial (PDF). Refer to the block diagram below for an overview of the design structure and the system components or cores included with the example.

Download the following files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Altera hardware reference design license agreement.

Block Diagram

View a detailed diagram including the signals in the design.

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.