OPRA FAST Parser Design Example

This example demonstrates an Open Computing Language (OpenCL*) implementation of a parser for the OPRA FAST standard. OPRA FAST is a standard developed for high-throughput and low-latency communication in financial markets; more information can be found at www.opradata.com.

The kernel parses incoming compressed OPRA Fast data from a UDP offload engine, and returns a subset of fields over Ethernet with the UDP offload engine. The UDP offload engines are represented as I/O channels to the kernel.

The kernel in this example is designed to process data at a line rate of 10G. More information is available in the OPRA FAST Overview and Implementation document available in the Downloads section below.


  • Channels vendor extension
  • Low-latency for latency-sensitive application
  • Single work-item kernel


The design example provides source code for the OpenCL* device (.cl) as well as the host application. For compiling the host application, the Linux package includes a Makefile.

The following downloads are provided for this example:

The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.

Software and Hardware Requirements

This design example requires the following tools:

  • Intel® FPGA Software v16.1 or later
  • Intel® FPGA SDK for OpenCL* v16.1 or later
  • Board package: must be compatible with Network Reference Platform
  • On Linux: GNU Make and gcc

To download the Intel design tools, visit the OpenCL* download page. Only the Linux operating system is supported by this design example

Specialized hardware may be required to achieve 10G link saturation in the host system. The following combination of hardware has been tested to achieve 10G saturation:

  • Solarflare SFN5122F Ethernet card
  • 2X Avago AFBR-709SMZ transceivers
  • Mellanox MAM1Q00A-QSA adaptors
  • Addon add-lc-lc-15m5om3 fiber optic cable

OpenCL* and the OpenCL* logo are trademarks of Apple Inc. used by permission by Khronos.

* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.