Continuously advancing semiconductor process technologies have increase component integration, functionality, and performance in embedded systems. While increased capabilities reap huge rewards, one side effect of higher-performance memory systems is that more attention must be paid to the probability of soft errors.
Decreasing supply voltages cause integrated circuits to be more susceptible to various types of electromagnetic and particle radiation. As DRAM memory size in embedded systems grows to 100s of megabytes, soft errors due to alpha particles that occurs naturally may exceed acceptable levels. As interface speeds exceed 1 Gbps, excessive noise and jitter may cause errors in the transmission lines to and from the external memory.
Error Resilience Through Error Correction Code
Driven by the increasing probability of soft errors, many designers are considering to add error correction code (ECC) to external DDR memory. ECC allows correction of single bit errors and drastically reduces the chance of a system failure. Altera® SoC devices are well positioned to support ECC, as all required logic functions are integrated into the device. ECC on external memory can be enabled simply by extending the width of the DDR memory, as shown in Figure 1.