Synthesis Resources Reports

Synthesis generates reports to display the following resource information based on the settings selected in the Compiler Settings page. Similar information is generated by the Fitter.

Resource Utilization by Entity Report

Reports the utilization of the following resources for each entity in the design logic cells, registers, memory bits, macrocells, DSP block elements, DSP block 9x9, 18x18, and 36x36 multipliers, virtual pins, pins, carry chain logic cells, logic cells that only utilize the look up table (LUT) in the logic cell, logic cells that only use the register, and logic cells that use both the register and the LUT. The specific resources listed in the Compilation Report might vary depending on the device selected.

The Compilation Report list can contain multiple Resource Utilization by Entity reports, one generated during Synthesis, partition based reports, and one generated during fitting. The Synthesis Resource Utilization by Entity report contains the resource usage of entities in the compilation hierarchy as calculated after logic synthesis, but before fitting. Because the Fitter's register packing Definition operation can reduce the number of logic cells in the design, the total usage reported in the Analysis & Synthesis Resource Utilization by Entity report may be greater than the total usage reported in the Fitter Resource Utilization by Entity report or the Fitter Resource Usage Summary report.


The Logic Cells, LUT-Only LCs, Register-Only LCs, LUT/Register LCs and Carry Chain LCs columns list the logic cells used by the design entity (including the top level design entity and all sub-entities) and the number of logic cells (in parentheses) used by the design entity at that level in the hierarchy.

The logic cell combinationals count may be inaccurate if the inputs or outputs of an entity are not registered. Having unregistered inputs and outputs can cause logic to be optimized across entity boundaries, which means that logic that was originally in one entity may be named after logic in an adjacent entity and may thus be accounted towards the wrong entity.

RAM Summary Report

Reports the following information about RAM memory in the design after Synthesis:

  • Name shows the name of the memory block.
  • Type shows the type of memory block you specified.
  • Mode shows the mode of the memory block: ROM, single-port, simple dual-port, true dual-port, or quad-port.
  • Port A Depth and Port A Width shows the depth (in bits) and width (in bits) of data port A.
  • Port B Depth and Port B Width shows the depth (in bits) and width (in bits) of data port B.
  • Size shows the size of the memory block in bits.
  • MIF shows the Memory Initialization File (.mif) Definition specified for the initial contents of the memory, if applicable.

IP Cores Summary Report

Reports the details on IP cores used in your design— including vendor, IP core name, version of the Quartus® Primesoftware when this core is created, release date, entity instance, license type, and the name and location of the IP include file.

Note: If the IP Cores Summary Report indicates that your IP core is outdated, you can update the IP core by opening the IP Catalog and selecting the option to Edit an existing custom Intel® FPGA IP variation.

DSP Block Usage Summary Report

Reports the operating modes and the number used of each type of DSP block Definition used by the design in supported device families, including multipliers, adders, accumulators, and DSP block 9-bit elements. This report appears only if the design includes DSP blocks.