To perform a simulation of a VHDL design with command-line commands using the Xcelium* simulator

  1. If you have not already done so, set up the Xcelium simulator working Environment.
  2. To create a work library in the project directory, type the following command at the command prompt:
    mkdir <work library>

    Intel recommends using the Xcelium (Verilog or VHDL) default library names when you create a library. You should name the Xcelium software libraries as follows:

    • When you run the Xcelium software independently from the Quartus® Prime software, you should name your library work.
    • When you run the Xcelium software automatically from the Quartus® Prime software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory when performing gate level simulation.
  3. Compile the library files with the following command line command:
    quartus_sh --simlib_comp -tool xcelium -family <device family>
      -language <language> -gen_only -cmd_file <simlib_device_family_file>
    This generates cds.lib, hdl.var, and simlib_device_family_file>.sh files. The <simlib_device_family_file>.sh contains the necessary library file commands.
  4. To compile the appropriate project files and libraries into the work library, type the following commands at the command prompt from within the project directory:
    xmvhdl <testbench file>.vhd  
    xmvhdl <project name>.vho
  5. To simulate high-speed circuits, including designs that use HSSI, LVDS, and PLLs,type the following command at the command prompt to enable transport delays:
    xmelab -pulse_e 0 -pulse_r 0 -timescale "1ps/1ps" work.<top-level entity name>
    Note: For more information about transport and inertial delays, refer to
  6. To elaborate and simulate the design, type the following commands at the command prompt:
    xmelab  <work library>.<top-level entity name>    
    xmsim <work library>.<top-level entity name>
  7. To direct the Xcelium software to generate a .vcd that you can then use to perform power analysis in the Quartus® Prime Power Analyzer:
    1. In the file explorer pane, select the <testbench or design instance name>_dump_all_vcd_nodes.tcl generated by the Quartus® Prime EDA Netlist Writer.
    2. On the File menu, click Source. The .tcl directs the Xcelium software to monitor and write the output signals contained in the .tcl to a .vcd during simulation.