Virtual JTAG Settings Report:

Reports information about instances of the sld_virtual_jtag Intel® FPGA IP present in the design:

  • Instance Index: Order assigned to the instance by the Quartus® Prime software.
  • Auto Index: Shows whether the Auto Index feature is enabled.
  • Index Reassigned: Shows whether the index was reassigned by the Quartus® Prime software due to a conflict in the design.
  • Address: Instance address.
  • USER1 DR length: Length of the data register targeting the USR1 JTAG instruction for the instance.
  • VIR capture instruction: Virtual instruction register capture instruction value for the instance.
  • IR Width: Width of the instruction register in bits.
  • Hierarchy Location: Hierarchy level in which the sld_virtual_jtag Intel® FPGA IP is instantiated.