Signal Tap Logic Analyzer Instances Instantiated in Design Settings Report

Reports information about instances instantiated in a design with the sld_signaltap Intel® FPGA IP. This report is created during Analysis & Synthesis.

  • Instance Index: Order assigned to the instance by the Quartus® Prime software.
  • Instance Name: Name of the instance as modified by the user.
  • Trigger Input Width: Width of the acq_trigger_in, in bits, that connects to the triggering logic.
  • Data Input Width: Width of the acq_data_in, in bits, that connects to the acquisition memory.
  • Sample Depth: Number of samples that can be acquired.
  • Trigger Levels: Number of sequential trigger condition levels.
  • Advanced Trigger Levels: Number of advanced trigger condition levels in a series you set for sampling.
  • Trigger In Used: Shows whether the trigger_in is connected.
  • Trigger Out Used: Shows whether the trigger_out is connected.
  • Hierarchy Location: Hierarchy level in which the sld_signaltap Intel® FPGA IP is instantiated.