SystemVerilog Synthesis Support

Quartus® Prime synthesis supports the following Verilog HDL language standards:

  • SystemVerilog-2005 (IEEE Standard 1800-2005)
  • SystemVerilog-2009 (IEEE Standard 1800-2009)
  • SystemVerilog-2012 (IEEE Standard 1800-2012)

The following important guidelines apply to Quartus® Prime synthesis of Verilog HDL and SystemVerilog:

  • The Compiler uses the SystemVerilog standard for files with the extension of .sv.
  • If you use scripts to add design files, you can use the -HDL_VERSION command to specify the HDL version for each design file.
  • The Compiler supports the include compiler directive to include files with absolute paths (with either “/” or “\” as the separator), or relative paths.
  • When searching for a relative path, the Compiler initially searches relative to the project directory. If the Compiler cannot find the file, the Compiler next searches relative to all user libraries. Finally, the Compiler searches relative to the current file's directory location.
  • Quartus® Prime Pro Edition synthesis searches for all modules or entities earlier in the synthesis process than other Quartus software tools. This earlier search produces earlier syntax errors for undefined entities than other Quartus software tools.

Quartus® Prime support for SystemVerilog is described for the following categories of SystemVerilog constructs. These sections match those in the IEEE Std 1800-2009 IEEE Standard for System Verilog Unified Hardware Design, Specification, and Verification Language manual. Refer to the Quartus® Prime Support for Verilog 2001 section below for information about supported Verilog 2001 features.