The Quartus® Prime software provides a variety of primitive functions for circuit design. AHDL, Verilog HDL, and VHDL logical operators, ports, and some statements, as well as Verilog HDL gate primitives, replace primitives in AHDL, Verilog HDL, and VHDL files. As a result, AHDL, Verilog HDL, and VHDL primitives are a subset of those available for Block Design File (.bdf) Definition, as shown below.

  • AHDL Function Prototypes are not needed for primitives in Text Design File (.tdf) Definition and Verilog Design File (.v) Definition. In AHDL, however, you can redefine the calling order of the primitive inputs by including a Function Prototype Statement for the primitive in the Text Design File.
  • Verilog HDL also includes built-in gate primitives that must be used instead of their corresponding Quartus primitives. Go to Using a Verilog HDL Gate Primitive for more information.