Creating and Instantiating a VHDL Function for Use with the Synplify Software

You can create or modify design files that contain custom Intel® FPGA IP variations of IP cores. You can then instantiate the custom IP variations in a design file for use with the Synopsys® Synplify and Quartus® Prime software. This procedure shows only how to instantiate a PLL function using VHDL; however, you can use similar procedures to instantiate other Intel-provided functions.

  1. If you have not already done so, set up the Synplify working environment.
  2. If you have not already done so, create a design for use with the Synplify software.
  3. Open the IP Catalog and specify appropriate options for the Intel® FPGA IP you want to instantiate.
  4. The IP Catalog generates custom Intel® FPGA IP variations that are based on provided functions, including library of parameterized modules (LPM) functions, as well as other IP cores.
  5. If necessary, perform a functional simulation of the design using an EDA simulation tool.
  6. Generate Verilog Quartus Mapping files with the Synplify software.
  7. If you have not already done so, create a new project or open an existing project.
  8. Compile the design in the Quartus® Prime software.