Creating a Design for Use with the Precision RTL Synthesis Software

With the Mentor Graphics® Precision RTL Synthesis working environment, create a design using Verilog HDL or VHDL.

  1. Enter a VHDL or Verilog HDL design in the Quartus® Prime Text Editor or another standard text editor and save it in your working directory.
    The Precision RTL Synthesis software automatically recognizes certain types of HDL code and maps them to Intel FPGA IP cores during synthesis. You can describe the design in Verilog HDL or VHDL and use the Precision RTL Synthesis software to infer multipliers, multiply-accumulators, multiply-adders, RAM, and ROM functions directly from HDL code.
  2. To include Intel® FPGA IP in your design, use the IP Catalog to generate and instantiate a Intel® FPGA IP variation. Additionally, you can use the IP Catalog to create LVDS or RAM Definition functions.
After creating your design, set your project with the Mentor Graphics® Precision RTL Synthesis software.