Performing a Gate-Level Functional Simulation with the QuestaSim Software

You can run the Mentor Graphics® QuestaSim software to perform a gate-level functional simulation of a VHDL or Verilog HDL design from the QuestaSim GUI or with command-line commands.

Note: For more information about using EDA simulators, refer to the Quartus® Prime Pro Edition User Guide: Third-party Simulation.