TMC-20050: RAM Control Signals Driven by LUTs or ALMs instead of DFFs


Violations of this rule identify combinational signals that drive the control signals of a number of RAM blocks beyond the value of the RAM_Inference_Logic_Threshold parameter. These signals are often the source of timing closure issues because RAM blocks are often difficult to localize around the signal source during Placement.


Name Description Type Default Value Min Value Max Value
RAM_Inference_Logic_Threshold Logic threshold in RAM Inference integer 100   0


Remove combinational statements in driving RAM control signals, register the output of the combinational logic if the extra latency can be tolerated, or duplicate the logic driving each signal to localize its fanouts to a smaller number of RAM blocks.




Tag Description
ram Design rule checks related to M20k blocks inside the FPGA fabric.

Device Family

  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®
  • Intel®Stratix® 10