RES-50001: Asynchronous Reset Is Not Synchronized


Violations of this rule identify unsynchronized asynchronous reset signal sources that reset registers. When using an asynchronous reset, the release of the reset signal must be synchronous with the register being reset. Otherwise, the register may experience metastability upon reset release.

Design Assistant can identify a reset transfer as asynchronous under any of the following conditions:

  • The reset signal is from an unconstrained input
  • The clock domain of the reset signal is unrelated or asynchronous to the latching domain of the register being reset
Figure 1. Unsynchronized Reset Example.. The following figure shows an unsynchronized reset that triggers Design Assistant violation RES-50001. To prevent the violation, the asynchronous reset must feed a reset synchronizer chain, the output of which can reset the register.


Synchronize the release of asynchronous reset signals with a reset synchronizer chain. Ensure that the reset signal feeds the asynchronous reset pins of a sequence of two or more registers, with no fan-out in between them, and with the head of the chain fed by a constant. You can use the output of the last register as a reset signal that is synchronous with the clock domain of the chain.

Figure 2. Synchronized Reset Example.. The following figure shows an asynchronous reset passed through a reset synchronizer chain. The output of the chain acts as a reset signal whose release has been synchronized to clk , and thus may be safely used to asynchronously reset registers latched by clk .




Tag Description
synchronizer Design rule checks related to synchronizer chains.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®