LNT-30024: LUT With More Than 1 Input Driving Clock Pins


Violations of this rule identify lookup tables that combine more than one input signal and drive into clock pins of registers. Any time a lookup table has multiple inputs, there is a risk of signal transitions arriving at those inputs at different times and creating glitches at the LUT output. These relative delays may differ between compiles as the optimization solution changes.

Without careful consideration and timing constraints, glitches on clock signals can result in spurious rising or falling transitions and cause registers to capture data erroneously.


If the violating LUT is gating the clock signal, consider re-implementing the logic that gates the clock as a clock enable signal on the destination registers instead.

If the violating LUT cannot be removed (for example, if it implements a clock mux), ensure that the structures feeding it are designed to be glitch-free and it is properly timing constrained and then waive its violation.




Tag Description
nonstandard-timing Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic.

Device Family

  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®
  • Intel®Stratix® 10
  • Intel®Arria® 10
  • Intel®Cyclone® 10 GX