LNT-30021: Same Signal Source Drives More Than One Asynchronous Port of a Register


Violations of this rule identify registers that have a common signal source driving into multiple asynchronous ports on the same register. This can result in signal races on the release of the asynchronous signals.

Figure 1. Multiple Synchronous Ports Driven By the Same Signal


Ensure that the asynchronous signals that drive into each violating register are registered independently and do not have a common combinational logic source.




Tag Description
nonstandard-timing Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic.

Device Family

  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®
  • Intel®Cyclone® 10 GX
  • Intel®Stratix® 10
  • Intel®Arria® 10