CDC-50103: Unsynchronized Intra-Clock Forced Synchronizer


Violations of this rule identify unsynchronized single-bit CDC transfers whose destination register is fed by data from the same clock domain, and is forced to be the head of a synchronizer chain by the assignment SYNCHRONIZER_IDENTIFICATION FORCED .

Figure 1. A sequence of intra-clock transfers where multiple registers are forced to be start of a synchronizer chain.


Violations of this rule typically indicate that all registers in a synchronizer chain have the assignment SYNCHRONIZER_IDENTIFICATION FORCED applied. If this is true, modify the assignments so that SYNCHRONIZER_IDENTIFICATION FORCED is only applied on the head register of a synchronizer chain. Otherwise, add synchronization registers after the head register of the unsynchronized intra-clock synchronizer chain.




Tag Description
synchronizer Design rule checks related to synchronizer chains.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®