CDC-50001: 1-Bit Asynchronous Transfer Not Synchronized


Violations of this rule identify a single-bit asynchronous data transfer not followed by a synchronizer chain. Such transfers may experience metastability.

A data transfer is considered asynchronous if its launch and latch clocks are unrelated or asynchronous. Clocks are unrelated if they do not share a common parent clock. Clocks are asynchronous if they are explicitly designated as such via a clock group or clock-to-clock false path. Data transfers are also asynchronous if their destination register has the SYNCHRONIZER_IDENTIFICATION FORCED instance assignment.

Figure 1. Unsynchronized 1-bit asynchronous transfer.


Protect single-bit asynchronous data transfers by a synchronizer chain. To do this, ensure that the destination of an asynchronous transfer forms a chain of two or more registers, with each register in the same clock domain as the destination of the transfer, and with no combinational logic between any of the registers in the chain. Also, ensure that there is no combinational logic on the path to the first register in the chain.

To confirm whether the chain is long enough to prevent metastability, run the report_metastability command in the Timing Analyzer.

If you do not intend a violating transfer to be asynchronous, ensure that the launch clock of the transfer is correct and is related to the latch clock of the transfer.

Figure 2. 1-bit asynchronous transfer synchronized by a two-stage synchronizer chain.




Tag Description
synchronizer Design rule checks related to synchronizer chains.

Device Family

  • Intel®Cyclone® 10 GX
  • Intel®Arria® 10
  • Intel®Stratix® 10
  • Intel Agilex®
  • Intel Agilex®
  • Intel Agilex®