The use of this design is governed by, and subject to, the terms and conditions of the Hardware Reference Design License Agreement.
The Octera XAUI SPI-4.2 Bridge provides a customizable framework to act as a starting point for more complex FPGA-based packet processing solutions for bridging applications. The design framework offers a highly optimized bridge function from custom XAUI to single or multi-channel SPI-4.2 ports.
For more complex FPGA designs, Octera uses a range of tools suitable for developing packet coprocessing in an overall system, perhaps containing a network processor or customer ASIC. These include a traffic generator, a library of C++ models of common packet processing functions, bus functional models, a complete register transfer level (RTL) environment, and a hardware platform. This allows you to model the FPGA packet processing in your own environment and then to generate a model of the required FPGA. Octera supplies RTL source code of base modules or customizes the modules on the your behalf.
- Supports 10 GbE, custom XAUI including Broadcom HiGig, HiGig+ protocols and will support emerging HiGig2 protocols
- Supports user-defined headers
- Programmable 1-18 PL4 channels
- Offers common packet processing, header extraction/insertion, tag insertion/deletion, VLAN processing, packet reassembly and priority queuing, and scheduling
- Customizable modular design
- C++ environment allows modeling of FPGA design in overall system
Figure 1 shows the block diagram of a fully populated Octera SPI-4.2-to-XAUI bridge transmit and receive path.
Figure 1. Octera SPI-4.2-to-Xaui Bridge Reference Design
- FC = Fibre Channel
- PL4 = POS-PHY Level 4
- CRC = Cyclic Redundancy Check
- PCS = Physical Coding Sublayer
Depending on the modules used, the design fits in:
- EP2SGX30F780C5N devices for HiGig protocol (C4 for HiGig+) in a basic configuration
- EP2SGX60F780C5N devices for HiGig protocol (C4 for HiGig+) for a more complex configuration
Demonstrated Intel Technology
- Source code of the specified customer design
- Test bench,including
- Traffic generation
- System modeling
- Bus functional modules including XAUI, XGMII, PL4, and Avalon® host buses
- Script interface
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