Intel® FPGA IP for HDMI
The Intel® FPGA Intellectual Property (IP) for High-Definition Multimedia Interface (HDMI) provides support for the next generation of video display interface technology. Due to its ability to send high-definition audio and video, HDMI has become the most common digital connection in consumer electronics.
The HDMI cable and connectors carry four differential pairs that are composed of three data channels and one clock channel. You can use these channels to carry video, audio, and auxiliary data at a raw bit rate of up to 3.4 Gbps or 6 Gbps per channel. HDCP-encrypted transmission can also be integrated into our IP through one of Intel’s partners. For more information, contact Bitec.
The following video demonstrates 4Kp60 resolution display using our HDMI IP core on the Stratix® V GX Development Kit.
IP Core Feature |
Description |
|---|---|
Color support |
|
Symbols per clock |
1, 2, or 4 symbols per clock |
Audio |
2 or 8 channels of embedded audio |
| Device Family | One Symbol per Clock Maximum Data Rate |
Two Symbols per Clock Maximum Data Rate |
Four Symbols per Clock Maximum Data Rate |
HDMI Version |
|---|---|---|---|---|
| Intel® Stratix® 10 | Not supported |
5,940 Mbps |
Not supported |
v.1.4 and v2.0 |
Intel Arria® 10 |
Not supported |
5,940 Mbps |
Not supported |
v.1.4 and v2.0 |
| Intel Cyclone® 10 | Not supported |
5,940 Mbps |
Not supported |
v.1.4 and v2.0 |
Stratix V |
2,970 Mbps |
5,940 Mbps |
Not supported |
v1.4 and v2.0 |
Arria V |
1,875 Mbps |
3,276.8 Mbps |
5,940 Mbps |
v1.4 and v2.0 |
Basics |
|
|---|---|
Year IP was first released |
2014 |
Latest version of Intel® Quartus® software supported |
18.0 |
Status |
Production |
Deliverables |
|
Customer deliverables include the following:
|
|
Any additional customer deliverables provided with IP |
None |
Parameterization GUI allowing end user to configure IP |
Yes |
IP core is enabled for Intel FPGA IP Evaluation Mode Support |
Yes |
Source language |
Both Verilog and VHDL |
Testbench language |
Both Verilog and VHDL |
Software drivers provided |
Verilog |
Driver operating system (OS) support |
N/A |
Implementation |
|
User interface |
Other (Video Data) |
IP-XACT metadata |
No |
Verification |
|
Simulators supported |
ModelSim, VCS, Riviera-PRO, NCSim (Verilog) |
Hardware validated |
Intel Stratix® 10, Intel Arria® 10, Intel Cyclone® 10, Stratix V, Arria V |
Industry standard compliance testing performed |
Yes |
If Yes, which test(s)? |
HDMI Source/Sink Compliance Test CTS 2.0b |
If Yes, on which Intel FPGA device(s)? |
Intel Arria 10 |
If Yes, date performed |
2017 |
If No, is it planned? |
N/A |
Interoperability |
|
IP has undergone interoperability testing |
Yes |
If yes, on which Intel FPGA device(s) |
Intel Stratix 10, Intel Arria 10, Intel Cyclone 10, Stratix V, Arria V |
Interoperability reports available |
Contact Sales |
Development Kits
The following development kits are available from Intel and Intel® partners for you to get started on your designs.
FPGA Board |
On-board HDMI Interface |
BITEC Daughtercard |
|---|---|---|
Not Available |
FPGA mezzanine card (FMC) daughtercard Transceiver (TX) and receiver (RX) |
|
| Stratix® 10 GX FPGA Development Kit | Not Available |
TX and RX |
| Cyclone® 10 GX FPGA Development Kit | Not Available |
TX and RX |
TX only |
High-speed mezzanine card (HSMC) daughtercard TX and RX |
|
No |
Design Examples
The following design example is available for you to run on the development kits. The block diagram is shown below.
Complexity |
Design Example |
Boards Supported |
|---|---|---|
Basic |
HDMI Hardware Demonstration for Arria V and Stratix V Devices chapter of the Intel FPGA HDMI IP Core User Guide |
Arria 10 GX FPGA Development Kit, Stratix V GX FPGA Development Kit, Arria V GX FPGA Development Kit |
| Intel Arria 10 UHD Video Reference Design | Arria 10 GX FPGA Development Kit |
Additional support for this Intel® FPGA IP core is available in the mySupport online issue tracking system.