インテル® SoC EDS サポート

Title Details

Intel® SoC FPGA Embedded Development Suite (SoC EDS) 19.1 Release Notes 

The Intel® SoC FPGA Embedded Development Suite (SoC EDS) Release Notes provides information about the most current release of the SoC EDS Professional Edition and the SoC EDS Standard Edition software. This document contains versions 18.0 and 18.1 of the Intel® SoC FPGA Embedded Development Suite Release notes.
Intel SoC FPGA Embedded Development Suite (SoC EDS) User Guide - 19.1 Edition This guide provides a complete introduction to all the features in the SoC EDS. It contains instructions on how to install the Intel SoC FPGA EDS, how to run the ARM DS-5* compiler, and includes Getting Started Guides for the main SoC EDS features (board set up running the tools, second stage bootloader, Bare-Metal debugging, Hardware Libraries)  
Intel SoC FPGA Embedded Development Suite (SoC EDS) Getting Started Guide Wiki 
This wiki describes the procedures users follow to help with board setup. It contains instructions on various SoC EDS features, including: how to run Linux*, how to get started with the Hardware Library Bare-Metal development, and how to run other tools such the Arm* DS-5 AE Eclipse*.
FPGA Adaptive Software Debug and Performance Analysis  This white paper outlines Intel and Arm’s* latest innovations in on-chip debug logic, FPGAs, and software debug and analysis tools aimed at addressing these challenges.
System Trace Macrocell Packs Major Benefits for High-Performance SOC System Debug 

This white paper introduces why the CoreSight* System Trace Macrocell (STM) is superior to an Instrumentation Trace Macrocell (ITM). 

 

Intel® Stratix® 10 SoC FPGA Technical Overview
Running the Preloader with the ARM DS-5* Debugger
Step-by-Step Installation of SoC EDS in Linux* Operating System
Booting Linux* in Intel® Stratix® 10 SoC
How to Write and Run a Bare-Metal C Program in ARM DS-5* AE for Intel® SoCs
Arria 10 SoC External u-boot Configuraiton for hte Golden System Reference Design
JTAG External Trace on Intel® SoCs using DSTREAM*
Gettng Started with Linux* on a Cyclone V SoC

Visit our Intel® FPGA Design Examples Support Page for more design examples.

SoC design examples are ready-to-use hardware and software projects that can be starting points to use and evaluate the features of Intel® SoC FPGAs.

Our series offers a balance of hardware performance, low power, form factor, and cost. Since our SoCs integrate many hard intellectual property (IP) blocks, you can use them to lower your overall system cost, power, and design time.

The design examples provided target the following development kits:

Each design example includes a design archive and readme.txt file. For each design, instructions on importing the design archive, compiling the design software, running the executable, and the expected terminal output are all provided in the readme.txt file.

Other design examples can be found on the SoC RTOS and HWLIBs support page as well as on Rocketboards.org

SoC Design Examples

Design Name Description File/Webpage Readme
SDMMC GSRD The Golden System Reference Design (GSRD) provides essential hardware and software system components that can be used as a starting point for various custom user designs. User Manual Arria 10 -
QSPI GSRD

Example

Arria 10

-
SGMI GSRD Release Notes Arria 10 -
Remote Update This project provides an example on how the user can remotely update the hardware and software running on an Altera Arria 10 SoC through a web interface.

Example

Arria 10

-
Remote Debug This example explains how to perform remote system debugging with the System-Level Debugging (SLD) tools.

Example

Arria 10

-
HPS-to-FPGA Bridges This design example exercises the memory mapped interfaces of the hard processor system (HPS) exposed to the FPGA fabric. The design performs memory tests by writing and reading the HPS memory using various ports of the HPS and measures the performance of the data movements.

Example

Readme-A10

Readme-CV

PCIe Root Port This reference design demonstrates a PCIe root port running on an Arria 10 SoC Development Kit connected to either a Cyclone V GT FPGA Development Kit PCIe end point or a generally available Intel PCIe Ethernet adapter card end point. It is also applicable on Cyclone V SoC Development Kit and Arria V SoC Development Kit.

Example

Arria 10

Arria V

Cyclone V

-
Secure Boot This document provides methods and design examples for implementing an Arria 10 SoC secure boot system using tools from the SoC Embedded Design Suite (SoC EDS) to secure the second-stage boot loader image.

Example

Arria 10

-
HPS DMA This HWLIB design example demonstrates how the DMA APIs are used to initialize the DMA, perform memory to memory transfers, and zero to memory transfers.

Example-AV
Example-CV
Example-A10

Readme-AV
Readme-CV
Readme-A10

Error correction code This HWLIB design example demonstrates the error correction code (ECC) APIs features for on-chip RAM, SD/MMC, quad serial peripheral interface (SPI), DMA and L2 cache. The example shows how to setup and enable ECC for each RAM, inject single/double bit errors and setup the interrupts for single/double bit error detections.

Example-AV
Example-CV
Example-A10

Readme-AV
Readme-CV
Readme-A10

GPIO This HWLIB design example demonstrates the usage of general-purpose input/output (GPIO) APIs to setup GPIO as output ports to drive HPS LEDs, and to setup GPIO as input ports for HPS push buttons. Example-AV
Example-CV
Example-A10
Readme-AV
Readme-CV
Readme-A10
I2C This HWLIB design example demonstrates the usage of I2C APIs to perform master read/write and slave read/write. This example demonstrates I2C communication with LCD screen, EEPROM memory as well as communication between two I2C modules. Example-AV
Example-CV
Example-A10
Readme-AV
Readme-CV
Readme-A10
Quad SPI This HWLIB design example demonstrates the usage of quad SPI APIs to perform reading and writing to the quad SPI with generic block I/O functions, perform data transactions using indirect mode and DMA mode. The example also demonstrates additional API features such as setting up MMU and caches. Example-AV
Example-CV
Readme-AV
Readme-CV
SD/MMC This HWLIB design example demonstrates the usage of SD/MMC APIs to initialize SD/MMC card, read and write using block I/O functions. Example-AV
Example-CV
Readme-AV
Readme-CV
Timer This HWLIB design example demonstrates how to use the Timer APIs for free-running timer, one-shot timer, watchdog timer, and global timer measurements. Example-AV
Example-CV
Example-A10
Readme-AV
Readme-CV
Readme-A10
Unhosted This HWLIB design example shows how to use UART for printf output instead of semihosting. It also demonstrates how to boot a bare-metal program from a SD card. Example-AV
Example-CV

Readme-AV
Readme-CV

SPI This HWLIB design example demonstrates the usage of the SPI APIs to communicate between two SPI modules connected through the FPGA fabric.

Example-AV
Example-CV
Example-A10

Readme-AV
Readme-CV
Readme-A10
HPS Peripheral Mapping to FPGA This design example shows how to route the hard processor system (HPS) EMAC and I2C peripherals into the FPGA fabric and connect them to FPGA I/O. Example Readme
Power Optimization This HWLIB design example illustrates the use of WFI or WFE calls that put the calling processor core into clock gating mode to save power. Example Readme
Shared Memory Partition  This design examples illustrates how to configure and test the memory protection rules for the hard processor system (HPS) SDRAM Controller. Example Readme

Foundational Training

Software Design Flow for an Arm*-based SoC (online, 27 minutes)

This course is intended for low-level software and firmware engineers. It examines the design flow required to implement software for an Intel® SoC with the Arm*-based hard processing system (HPS). 

 

Getting Started with Linux* OS for Intel® SoC FPGAs (online, 37 minutes)

This course presents various Linux options available for Intel SoC FPGAs with integrated Arm Cortex* processors. You'll get an overview of the software development flow needed to create a Linux* application. Then learn the details on the various Linux versions supported including, the latest stable kernel, the Long-Term Support Initiative (LTSI), and LTSI with real-time patches. 

 

Intermediate Training  

Developing an Arm*-based SoC (instructor-led, 8 hours) 

This course is for firmware and low-level software engineers, and teaches software bring-up and development on the embedded ARM Cortex-A9 hard processor system (HPS) in an SoC.

 

SoC Bare-Metal Programming and Hardware Libraries (online, 28 minutes)

This course discusses how to use the tools and features available in the Intel SoC Embedded Design Suite to successfully develop a bare-metal application for Intel Arm*-based SoC devices.

 

Creating Second Stage Bootloader for Intel® SoCs (online, 31 minutes)

This course discusses how to use the tools and features available in the Intel SOC Embedded Design Suite, to successfully customize and generate a second stage bootloader for Arm*-based SoC devices.

 

Secure Boot with the Intel® Arria® 10 SoC FPGAs (online, 17 minutes)

This course discusses the secure boot options available with the Intel Arria® 10 SoC FPGAs with the Arm*-based hard processing systems (HPS) 

 

WS1 Intel SoC Device Introduction for Software Developers (Rocketboards.org)

This is the first section in the Intel SoC Workshop Series designed to help users become familiar with software development for the Intel SoC family. This workshop will cover basic SoC architecture, address maps, as well as hardware and software tool flows. 

 

WS2 Linux Kernel Introduction for Intel® SoC Devices (Rocketboards.org)

This is the second section in the Intel® SoC Workshop Series. This section takes you through the steps of building the SoC FPGA-specific pieces of a custom embedded Linux distribution. It is intended to familiarize you with the resources necessary to build an embedded Linux distribution for your own SoC FPGA-based board.

 

WS3 Developing Drivers for Intel® SoC Linux (Rocketboards.org)

This is the third section in the Intel SoC Workshop Series. This section provides an overview of the SoC Linux driver development concepts.

 

Other Recommended Training